BFD/RISC-V: Zve{32,64}f do not need to explicitly imply Zvl{32,64}b
Removes redundant RISC-V CPU extension implications in BFD to avoid excess processing.
This patch simplifies RISC-V CPU extension handling in binutils’ BFD library. It removes explicit implications for Zvl{32,64}b when Zve{32,64}f extensions are present. The existing Zve{32,64}x implications already cover the necessary dependencies, making the explicit Zvl settings redundant and subject to excess processing.
In Details
In binutils' BFD library, this patch refines the RISC-V CPU extension handling logic within elfxx-riscv.c. It modifies the riscv_implicit_subset_map to remove redundant explicit dependencies of zve64f on zvl64b and zve32f on zvl32b. Since zve64x and zve32x already imply zvl64b and zvl32b respectively, these specific subsets no longer need to be explicitly listed under zve64f and zve32f.
- BFD
- The Binary File Descriptor library, a low-level interface for manipulating object files and archives. It supports various object file formats like ELF and a.out.
- RISC-V
- An open-standard Instruction Set Architecture (ISA) based on reduced instruction set computing principles. It is known for its modularity and extensibility.
- Zve{32,64}f
- RISC-V extension for single-precision (32-bit) and double-precision (64-bit) floating-point operations.
- Zvl{32,64}b
- RISC-V extension for 32-bit and 64-bit vector operations.
- Zve{32,64}x
- RISC-V extension for 32-bit and 64-bit vector-integer operations.
- Instruction Set Architecture (ISA)
- The part of the processor architecture visible to the programmer or compiler. It defines the set of instructions a CPU can execute.
- Implication
- In the context of CPU extensions, an implication means that enabling one extension automatically enables others that depend on it.