RISC-V: check operands for Zqinx
Add operand checks for the RISC-V Zqinx extension in RV32 and RV64.
This patch introduces operand checks for the RISC-V Zqinx extension in both RV32 and RV64. It enforces that register pair operands must have specific low bits clear: the least significant bit for RV64 and the two least significant bits for RV32. This validation is crucial for correct instruction encoding, especially since the Zqinx extension’s exact specifications for register pairs are not formally defined.
- proposer
Introduces register pair operand checks for Zqinx in RV32 and RV64.
“By analogy to Zdinx on RV32, register pair operands are presumably (there not being any formal spec afaict) required to be encoded with the low bit clear in RV64; in RV32 the low two bits need to be clear. Since match functions don't have XLEN available, introduce respective flags, to be used explicitly in assembler and disassembler.”
- reviewer
Questioned the utility of Zqinx in RV32, noting that it leads to awkward function argument passing and that it cannot be enabled with the V extension.
Technical Tradeoffs
- Improves correctness by enforcing operand constraints for the Zqinx extension.
- Relies on inferred rules due to the lack of formal specification for Zqinx register pair encoding.
In Details
This patch refines the RISC-V assembler's instruction decoding for the Zqinx extension. It adds validation for register operands used in pairs, requiring specific bit patterns (even for RV64, low bit clear; for RV32, low two bits clear) based on perceived common practice due to lack of formal specification. This ensures that instructions are correctly assembled according to implied constraints for critical extensions.
- RISC-V
- An open-source instruction set architecture (ISA) that is gaining popularity for its modularity and extensibility.
- Zqinx
- A RISC-V extension that provides integer multiplication instructions.
- RV32
- The 32-bit variant of the RISC-V architecture.
- RV64
- The 64-bit variant of the RISC-V architecture.
- XLEN
- The native integer width of a RISC-V processor, either 32 or 64 bits.