RISC-V: check operands for Zdinx in RV32
Add operand checks for the RISC-V Zdinx extension specifically for RV32.
This patch enhances the RISC-V assembler by adding operand checks for the Zdinx extension in RV32. Similar to the Zilsd extension, it enforces that register pair operands must have their least significant bit clear. This validation is implemented using a new RV32_EVEN_CHECK macro, ensuring correct instruction encoding for this extension.
- proposer
Introduces operand checks for Zdinx in RV32, requiring register pairs to have the LSB clear.
“Like for Zilsd, register pair operands are required to be encoded with the low bit clear. Since match functions don't have XLEN available, introduce respective flags, to be used explicitly in assembler and disassembler.”
- reviewer
Noted that similar checks could be applied to Zilsd, potentially reducing the need for some match functions. Also mentioned that scalar vector instructions lack similar encoding clarity, and V/Zdinx cannot be enabled together presently.
Technical Tradeoffs
- Ensures correct instruction encoding for Zdinx by validating register operands.
- Introduces a new macro (`RV32_EVEN_CHECK`), potentially duplicated or refactored later based on reuse with Zilsd.
In Details
This patch adds specific operand validation for the RISC-V Zdinx ('doubleword integer load/store') extension in the RV32 configuration. It enforces that register pairs used in Zdinx instructions must have the least significant bit (LSB) clear, a constraint derived from the instruction encoding. This validation is implemented via a new macro, RV32_EVEN_CHECK, ensuring that incorrect register pairings are caught during assembly.
- RISC-V
- An open-source instruction set architecture (ISA) that is gaining popularity for its modularity and extensibility.
- Zdinx
- A RISC-V extension for doubleword integer load and store instructions.
- RV32
- The 32-bit variant of the RISC-V architecture.
- LSB
- Least Significant Bit. The bit with the lowest value or position in a binary number.
- XLEN
- The native integer width of a RISC-V processor, either 32 or 64 bits.