RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
Remove redundant floating-point conversion instructions from RISC-V assembler.
This patch removes redundant forms of the RISC-V FCVT.Q.L and FCVT.Q.LU instructions from the assembler’s opcode table. These forms incorrectly allowed a floating-point rounding mode operand, which is not applicable to these specific conversions. The removal simplifies the opcode definitions and prevents incorrect instruction usage.
In Details
This patch cleans up the RISC-V opcode table by removing forms of fcvt.q.l and fcvt.q.lu that incorrectly included a rounding mode operand. These particular conversions operate on floating-point values being converted to integers, and the rounding mode specifier is not relevant. This cleanup ensures the assembler adheres to the RISC-V ISA specification for these instructions.
- RISC-V
- An open-source instruction set architecture (ISA) that is gaining popularity for its modularity and extensibility.
- FCVT.Q.L
- A RISC-V floating-point instruction for converting a quad-precision floating-point value to a long integer.
- FCVT.Q.LU
- A RISC-V floating-point instruction for converting a quad-precision floating-point value to a long unsigned integer.
- Rounding Mode
- Specifies how to handle the result of a floating-point operation when it cannot be represented exactly. Common modes include round-to-nearest, round-to-zero, etc.
- Opcode table
- A data structure used by assemblers and disassemblers to map instruction mnemonics to their binary representations.