RISC-V: make FP rounding mode an optional operand
Allow optional FP rounding mode operand for RISC-V instructions.
This patch modifies the RISC-V assembler to make the floating-point rounding mode operand optional for most instructions. This change simplifies the opcode table by reducing redundant entries and aligns the handling with similar ARM Vm and VM counterparts. The rounding mode is now implicitly handled unless explicitly specified, with an exception for FCVTMOD.W.D where ‘M’ is still required.
In Details
This change refactors the RISC-V assembler's instruction parsing for floating-point operations. It makes the rounding mode specifier ('m' or 'M') optional for most FP instructions, similar to how it's handled for 'Vm' and 'VM' instructions, reducing opcode table entries. The rounding mode is now implicitly determined if not provided, except for specific instructions like FCVTMOD.W.D that require explicit rounding mode specification.
- RISC-V
- An open-source instruction set architecture (ISA) that is gaining popularity for its modularity and extensibility.
- FP
- Floating-point. Refers to numbers with fractional parts, handled by dedicated hardware units in most processors.
- Rounding Mode
- Specifies how to handle the result of a floating-point operation when it cannot be represented exactly. Common modes include round-to-nearest, round-to-zero, etc.
- Opcode table
- A data structure used by assemblers and disassemblers to map instruction mnemonics to their binary representations.