x86: ACE_V1 support for ACE-specific instructions
Adds assembler and disassembler support for new ACE_V1 specific instructions, including block scale register operations and tile outer products.
This patch series extends binutils support for the ACE_V1 (AI Compute Extensions) ISA by adding assembler and disassembler logic for ACE-specific instructions. This includes operations involving the block scale register, tile move writes, and various outer product instructions, referencing the ACE v1.16.2 specification.
In Details
This is the second part of a series adding support for the ACE_V1 ISA to binutils. It focuses on the instructions unique to ACE, differentiating from the AMX-shared instructions covered in the first part. This includes instructions like BSRINIT, BSRMOVF/H/L for block scale registers, TILEMOVCOL/ROW for tile data movement, and several TOP variants for outer products. The implementation details in gas/ and opcodes/ are updated to recognize and correctly disassemble these new instructions based on the ACE v1.16.2 specification.
- ACE_V1
- AI Compute Extensions version 1, an instruction set architecture extension for AI workloads on x86 processors.
- EVEX
- An advanced instruction prefix used in x86 processors for SIMD operations, supporting features like extended registers, vector lengths, and masking.
- TMM
- Tile Matrix Multiply registers, used by AMX and other AI acceleration features on x86 processors.
- block scale register
- A register used in certain x86 instruction set extensions to control the scaling of blocks for operations like outer products.
- tile move write
- Instructions that move data into tile registers, often used in matrix operations.
- outer product instructions
- Instructions that compute the outer product of two vectors, a fundamental operation in linear algebra and machine learning.