x86: ACE_V1 support for AMX-shared instructions
Enables ACE_V1 architecture support in binutils, reusing AMX instructions for tile management and operations.
This patch introduces assembler and disassembler support for the ACE_V1 architecture in binutils, enabling its use alongside existing AMX-shared instructions. It allows TMM register usage and includes validation for EVEX.V’ encoding to reject invalid combinations, ensuring correct interpretation of these AI-focused instructions.
In Details
This is the first part of a series introducing ACE_V1 ISA support to binutils. It focuses on enabling the ACE_V1 architecture and reusing existing AMX (Advanced Matrix Extensions) instructions for tile management, row moves, and conversions. The changes include updating the configuration to recognize ACE_V1, modifying opcode tables and disassembler logic to handle these shared instructions with ACE_V1 context, and adding validation for the EVEX.V' encoding to prevent incorrect usage with specific register types.
- ACE_V1
- AI Compute Extensions version 1, an instruction set architecture extension for AI workloads on x86 processors.
- AMX
- Advanced Matrix Extensions, an x86 instruction set extension designed to accelerate matrix operations, particularly for AI and machine learning workloads.
- TMM registers
- Tile Matrix Multiply registers, a set of registers introduced with AMX for holding matrix tiles.
- EVEX
- An advanced instruction prefix used in x86 processors for SIMD operations, supporting features like extended registers, vector lengths, and masking.