TUESDAY, SEPTEMBER 29, 2026
x86 — Proposed
x86: add ACE V1 block scale register instructions
Adds assembler and disassembler support for ACE V1 block scale register instructions and the bsr0 register.
This patch introduces assembler and disassembler support for the BSRINIT, BSRMOVF, BSRMOVH, and BSRMOVL instructions, along with the bsr0 register. This is part of a larger series enabling the AI Compute Extensions (ACE) V1 ISA in binutils.
In Details
This patch adds support for new x86 instructions related to the ACE V1 specification, specifically focusing on block scale registers (bsr0). It modifies gas/config/tc-i386.c to recognize the bsr0 register and updates opcodes/i386-dis-*.h and opcodes/i386-opc.tbl to handle the new instructions within the gas and opcodes components of binutils.
For Context
- ACE V1
- AI Compute Extensions version 1, a set of x86 instructions designed to accelerate AI and machine learning workloads.
- assembler
- A program that converts assembly language source code into machine code.
- disassembler
- A program that converts machine code into assembly language source code.
- bsr0
- A register introduced with ACE V1, used in conjunction with block scale register instructions.
- gas
- The GNU Assembler, part of the GNU Binutils project.
- opcodes
- The part of an instruction that specifies the operation to be performed. In binutils, 'opcodes' refers to the component responsible for instruction decoding and encoding.