RISC-V: Zvfbfwma implies Zvfbfmin
Ensures the RISC-V assembler correctly recognizes that the Zvfbfwma instruction implies the Zvfbfmin extension.
This commit updates the RISC-V assembler’s understanding of instruction subset implications. Specifically, it corrects the definition so that the Zvfbfwma instruction is recognized as implying Zvfbfmin, aligning with the RISC-V specification. This ensures correct assembly and disassembly for RISC-V code using these vector extensions.
In Details
The RISC-V ELF object file format (BFD) now correctly encodes the implication that the Zvfbfwma instruction subset requires the Zvfbfmin extension. This change updates elfxx-riscv.c and gas/testsuite/gas/riscv/imply.d to reflect this required dependency, ensuring the assembler and disassembler correctly handle instruction sets that include Zvfbfwma.
- Zvfbfwma
- A RISC-V 'Z' extension that provides single-precision floating-point, byte-by-byte, fused multiply-add instructions.
- Zvfbfmin
- A RISC-V 'Z' extension that provides single-precision floating-point, byte-by-byte, multiply-add instructions.
- RISC-V
- A free and open Instruction Set Architecture (ISA) based on modularity, extensibility, and simplicity.
- BFD
- The Binary File Descriptor library, used by binutils to support various object file formats like ELF.