RISC-V: EEW64 checking for assembler and disassembler
Assembler and disassembler now correctly handle RISC-V instructions using EEW64 with the Zve64x extension.
This commit enhances RISC-V support by ensuring the assembler and disassembler correctly use the INSN_V_EEW64 flag. Instructions marked with this flag are now properly handled, preventing their disassembly when the Zve64x extension is not enabled. It also removes a redundant Zve32x check in the assembler, as Zve64x implicitly includes Zve32x.
In Details
The RISC-V assembler and disassembler have been updated to correctly interpret the INSN_V_EEW64 flag. This flag signifies instructions that use 64-bit Element Width (EEW) in vector operations. The change ensures these instructions are only recognized and processed when the zve64x extension is enabled, as required by the RISC-V specification. A redundant check for zve32x in the assembler has been removed because zve64x implies zve32x for all INSN_CLASS_V instructions.
- EEW64
- Element Width 64. Refers to a vector operation's width, where each element in the vector register is 64 bits wide.
- Zve64x
- A RISC-V 'Z' extension that adds 64-bit vector integer instructions.
- Zve32x
- A RISC-V 'Z' extension that adds 32-bit vector integer instructions.
- INSN_V_EEW64
- A flag indicating that a RISC-V instruction uses 64-bit Element Width for vector operations.
- RISC-V
- A free and open Instruction Set Architecture (ISA) based on modularity, extensibility, and simplicity.