RISC-V: Ensure Zv{b,k}* extensions imply Zve32x
RISC-V toolchain now correctly implements the Zve32x implication for Zv{b,k}* extensions as per specification.
The binutils BFD library now correctly reflects the RISC-V specification’s requirement that certain Zv extensions imply the Zve32x extension. This was achieved by reordering the riscv_implicit_subsets table to ensure that the Zv{b,k}* entries, which imply Zve32x, are processed before other entries that might be affected by this implication. A gas testsuite file was also updated to match.
In Details
The RISC-V BFD backend's riscv_implicit_subsets table defines how instruction set extensions imply each other. This commit corrects an ordering issue where Zv{b,k}* extensions, which should imply Zve32x according to the specification, were not correctly processed. By moving the Zv{b,k}* entries earlier in the table, the correct implication is now established, preventing potential misinterpretations of supported extensions. The gas testsuite was also updated.