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binutils/x86
Add ACE V1 support for AMX-shared instructions
Binutils assembler gains support for AMD's ACE V1 architecture, reusing AMX instructions.
This change enables support for the AMD AI Compute Extensions (ACE) V1 architecture within the x86 assembler. It allows ACE V1 to utilize existing AMX-shared instructions for tile management and TMM register usage, aligning with the ACE V1 specification.
In Details
Support for AMD's ACE V1 architecture is introduced by integrating its specifications into the x86 opcode tables and gas configuration. This involves enabling ACE V1 as a distinct CPU architecture and mapping its instruction set, particularly the tile management instructions, to the existing AMX-shared instruction set, ensuring correct encoding and decoding for TMM registers.
For Context
- ACE V1
- AI Compute Extensions version 1, an AMD architecture specification providing enhanced AI and machine learning capabilities on x86 processors.
- AMX
- Advanced Matrix Extensions, an x86 instruction set extension providing hardware acceleration for matrix operations, often used in AI/ML workloads.
- TMM
- Tile Matrix Math, a set of registers introduced with AMX for matrix operations.