Support for internal 'TILE' feature
Binutils introduces an internal 'TILE' pseudo-ISA for shared AMX tile instructions.
This commit adds an internal pseudo-Instruction Set Architecture (ISA) bit named ‘TILE’ to represent a shared subset of AMX tile instructions. This distinction is necessary because AMD’s ACE architecture shares some tile registers and instructions (LDTILECFG, STTILECFG, TILERELEASE, TILEZERO) with AMX_TILE, while others are exclusive to AMX.
In Details
An internal pseudo-ISA bit, 'TILE', is introduced to differentiate instructions and registers that are common between AMD's ACE and AMX_TILE features. This allows the assembler to correctly distinguish and encode instructions that are shared, such as tile configuration and management, from those specific to AMX_TILE, ensuring proper ISA handling.
- Pseudo-ISA
- An internal representation or flag within the assembler that denotes a specific set of instructions or features, which may not correspond to a formally defined hardware ISA.
- AMX_TILE
- A part of the Advanced Matrix Extensions (AMX) instruction set that deals with tile-based operations, used for matrix manipulations.
- ACE
- AI Compute Extensions, an AMD architecture that provides enhanced AI and machine learning capabilities.