WEDNESDAY, SEPTEMBER 2, 2026
risc-v
Add support for RISC-V XXTVarith and XXTVcoder extensions.
Binutils now supports the XuanTie XXTVarith and XXTVcoder RISC-V extensions.
This patch introduces support for the XuanTie vendor-specific XXTVarith and XXTVcoder extensions for the RISC-V architecture. These extensions include new vector instructions for arithmetic operations, Galois-field multiply-xor, and fast CRC folding, along with instructions similar to Zvabd.
In Details
This commit adds support for the XuanTie-specific RISC-V vector extensions XXTVarith and XXTVcoder. It updates bfd/elfxx-riscv.c to recognize the implications of these extensions in riscv_multi_subset_supports and adds new opcode definitions in include/opcode/riscv-opc.h. New gas test cases are also included.
For Context
- RISC-V
- A free and open instruction set architecture (ISA) based on Reduced Instruction Set Computer principles. It is designed to be simple, extensible, and suitable for a wide range of applications.
- XXTVarith
- A XuanTie vendor-specific extension for RISC-V that adds vector arithmetic instructions, including interleave, Galois-field multiply-xor, and fast CRC folding operations.
- XXTVcoder
- A XuanTie vendor-specific extension for RISC-V that adds vector instructions similar to those found in the Zvabd extension.
- Vector instructions
- Instructions that operate on multiple data elements simultaneously, enabling parallel processing for tasks like multimedia and scientific computing.