FRIDAY, SEPTEMBER 18, 2026
binutils/riscv Breaking Change
Revert RISC-V Zvabd extension support
Removes support for the unratified RISC-V Zvabd extension.
This commit reverts the addition of support for the RISC-V Zvabd extension. The extension is currently unratified and has undergone changes in its encoding and instructions. Removing support prevents issues with incomplete or unstable hardware features.
In Details
This commit removes the RISC-V Zvabd extension from BFD and GAS configurations. The Zvabd extension is marked as ISA_SPEC_CLASS_DRAFT, indicating it's under active development and not yet ratified by the RISC-V International committee. Reverting its support is necessary due to ongoing changes in its instruction encoding and instruction set.
For Context
- Zvabd
- A draft extension for the RISC-V instruction set architecture, related to vector operations, specifically 'vector dot product acceleration for unsigned integer vectors'.
- unratified
- Not yet officially approved or standardized by the relevant governing body (in this case, RISC-V International).
- instruction encoding
- The binary representation of a machine instruction, defining the operation to be performed and the operands involved.