x86: Optimize instruction template operand type storage
Reduces memory usage in x86 instruction parsing by sharing operand type combinations.
This commit optimizes the x86 instruction parser by moving the operand_types array out of struct insn_template. Instead, a global array i386_operand_types now stores all unique operand combinations, and struct insn_template stores an index to this array. This significantly reduces memory usage and redundancy, especially for instructions with common operand patterns, decreasing the number of stored operand types from over 10,000 to 770.
In Details
The insn_template structure in the x86 opcode table now stores an operand_ref index instead of directly embedding the operand_types array. A new global array i386_operand_types holds all unique operand type combinations, and the assembler uses a hash table to avoid duplicating identical combinations. This change, motivated by reducing redundancy and memory footprint, dramatically cuts down the number of distinct operand type sets.
- insn_template
- A data structure used in the assembler's opcode table to define the characteristics of an instruction, including its operands and how to encode it.
- operand_types
- An array within
insn_templatethat specifies the type and properties of each operand for a given instruction. - opcode table
- A data structure used by assemblers and disassemblers to map instruction mnemonics and their operand patterns to their machine code representations.
- x86
- A family of instruction set architectures (ISAs) originating from the Intel 8086 microprocessor. It is the most common ISA for desktop and server computers.