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OCTOBER 6, 2026
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risc-v

RISC-V: Add support for XAndesVPackFPH extension

Binutils now supports the RISC-V XAndesVPackFPH extension for packed floating-point instructions.

This commit adds support for the RISC-V XAndesVPackFPH extension, enabling packed FP16 fused multiply-add instructions. Updates were made to BFD for ELF handling, GAS for assembler directives and tests, and the opcode library for instruction recognition. This allows for more efficient floating-point operations on compatible Andes architectures.

In Details

This change introduces support for the XAndesVPackFPH extension into the RISC-V binutils. It involves modifications to BFD's riscv_multi_subset_supports functions to recognize the extension, updates to GAS for new assembly syntax and test cases, and additions to the opcode tables and instruction classes in opcode/riscv-opc.c and include/opcode/riscv.h. This expands the toolchain's capability for Andes-specific vector floating-point operations.

For Context
XAndesVPackFPH
A RISC-V extension from Andes Technology that enables packed FP16 (half-precision floating-point) fused multiply-add operations.
RISC-V
An open-standard Instruction Set Architecture (ISA) based on Reduced Instruction Set Computer principles.
BFD
The Binary File Descriptor library, used by binutils to handle various object file formats like ELF.
GAS
The GNU Assembler, part of binutils, responsible for translating assembly language into machine code.
ELF
Executable and Linkable Format, a common standard file format for object files, executables, and shared libraries on Unix-like systems.
FP16
A floating-point format using 16 bits, offering reduced memory usage and potentially faster computation compared to FP32 or FP64.
Filed Under: risc-vfloating-pointvector instructionsassembler