RISC-V tail pseudo instruction accepts optional register
RISC-V tail pseudo-instruction now accepts an optional register argument for scratch usage.
The RISC-V tail pseudo-instruction now supports an optional register argument, similar to the jump instruction. This allows compilers to emit software-guarded tail calls using a scratch register, ensuring compatibility with systems that may not have the Zicfilp extension enabled, by using an auipc hint encoding.
In Details
Adds support for tail <symbol>, <rt> to the RISC-V assembler. This new form is intended for compilers implementing software-guarded tail calls compatible with the Zicfilp extension's lpad instruction. It uses an auipc hint encoding, allowing it to function even when Zicfilp is not present in the ISA string, by using the specified register <rt> as a scratch register.
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computing principles.
- pseudo-instruction
- An instruction that is not part of the actual machine code but is recognized and expanded by the assembler into one or more machine instructions.
- Zicfilp
- A RISC-V base ISA extension that provides support for Procedure-Linkage Table (PLT) and indirect function calls, including optimized tail calls.
- auipc
- Add Upper Immediate to PC, a RISC-V instruction used for generating PC-relative addresses.
- tail call
- A function call that is the last operation in a function. Tail call optimization replaces the call with a jump, avoiding stack frame growth.