Optimize AArch64 ADD relocations resolving to zero
Optimize AArch64 ADD instructions with zero immediate operands after relocation.
This commit optimizes AArch64 ADD instructions where the immediate value becomes zero after relocation, as recommended by the ARM architecture specification. It replaces ADD x0, x1, 0 with MOV x0, x1 and ADD x2, x2, 0 with NOP, while handling register 31 (SP) and —no-relax appropriately. This improves code density and performance.
In Details
The AArch64 linker now optimizes ADD instructions that resolve to a zero immediate operand. For ADD Rd, Rn, #0 where Rd != Rn, it generates MOV Rd, Rn. For ADD Rd, Rd, #0, it generates MOV Rd, Rd (which is a no-op on 64-bit). This follows the ELF for the Arm 64-bit Architecture specification. The optimization is applied to all supported relocations and linker-generated PLT entries, respecting --no-relax for input relocations. Special handling is included for register 31 (SP) and 32-bit W registers.
- AArch64
- The 64-bit ARM architecture.
- ADD instruction
- A CPU instruction that performs addition.
- relocation
- A modification to code or data that is needed to allow a module to be shared by multiple processes or to be loaded at different addresses. The linker performs relocations.
- immediate operand
- A value that is part of an instruction itself, rather than being fetched from memory or a register.
- MOV instruction
- A CPU instruction that copies a value from one register to another.
- NOP instruction
- No Operation. A CPU instruction that does nothing.
- SP
- Stack Pointer. A special register that holds the address of the current top of the stack.
- --no-relax
- A linker option that prevents the linker from performing certain optimizations that might change the addresses of instructions or data.
- PLT
- Procedure Linkage Table. A table used in dynamically linked executables to resolve external function calls at runtime.