Tighten memory predicates and constraints for SH architecture
SH architecture memory access rules strengthened, especially with LRA.
This commit tightens memory predicates and constraints for the SH architecture, particularly for the Load-Ready-Access (LRA) register allocator. It rejects invalid hard registers for memory address registers when LRA is used, requiring stricter predicates and constraints. This change aims to ensure correct memory access patterns and prevent errors during code generation.
In Details
SH architecture's memory operand handling is refined by introducing new constraints (Rab, Rai, Sgb) and tightening existing ones. The simple_mem_operand now uses satisfies_constraint_Sra, while post_inc_mem and pre_dec_mem use satisfies_constraint_Rab. Additionally, GBR addresses are rejected for certain hard-llcs atomic operations when LRA is active, reflecting LRA's stricter requirements compared to the older reload mechanism.
- SH architecture
- A family of 32-bit microprocessors developed by Hitachi (now Renesas Electronics). GCC supports various SH processor cores.
- LRA
- Load-Ready-Access, a register allocator used in GCC. It aims to efficiently allocate registers during code generation.
- Predicates and Constraints
- In compiler theory, constraints define which operands are valid for a given instruction, while predicates are conditions that must be true for an operation to be valid. They help ensure correct instruction generation.
- GBR
- GBR (Global Base Register) is a register used in some architectures, including SH, for specific addressing modes or global data access. In this context, it's being restricted for certain atomic operations.