Add ARM SVE2p3 and SME2p3 conversion intrinsics.
New ARM intrinsics supporting SVE2p3 and SME2p3 conversion instructions are now available.
Support for new floating-point and integer conversion intrinsics has been added for the AArch64 architecture, specifically targeting the SVE2p3 and SME2p3 extensions. These intrinsics leverage the latest conversion instructions, enabling more efficient data type transformations for SIMD and scalable vector operations. Corresponding test cases have also been integrated.
In Details
This patch introduces new intrinsic functions and associated machine-dependent patterns in config/aarch64/ for AArch64's SVE2p3 and SME2p3 advanced SIMD and SVE features. It adds support for conversion intrinsics like cvtzn, cvttb, and their variants (e.g., svcvtn, svcvtt, svcvtb). These map to new conversion instructions available in SVE2p3/SME2p3, enabling type conversions between various floating-point and integer formats. Iterator definitions and test cases are updated accordingly.
- aarch64
- The 64-bit ARM architecture.
- SVE
- Scalable Vector Extension. An ARM instruction set extension that allows vector registers to vary in length, improving performance and code density for a wide range of applications.
- SME
- Scalable Matrix Extension. An ARM instruction set extension that complements SVE by providing support for matrix operations.
- intrinsics
- Special functions or constructs in a programming language that map directly to a specific hardware instruction or sequence of instructions. They provide C/C++ programmers access to low-level hardware capabilities.
- conversion instructions
- Machine instructions that change a value from one data type to another, such as converting an integer to a floating-point number or vice versa.