Convert fold-mem-offsets pass to use RTL-SSA
The fold-mem-offsets optimization pass is rewritten to use RTL-SSA, improving efficiency by processing instructions in a single pass.
The fold-mem-offsets optimization pass has been converted from using DF (Data Flow) to RTL-SSA (Register Transfer Language Static Single Assignment). This rewrite significantly alters how the pass collects information, now processing each instruction only once. It introduces single-USE and multi-USE modes for identifying foldable memory offsets, with performance varying based on code complexity and optimization level.
In Details
The fold-mem-offsets pass, previously operating on DF, is now ported to RTL-SSA. It analyzes RTL instructions to identify memory references of the form (*base_reg + offset) where the offset is a constant. The pass now iterates once over non-debug INSNs, building a DEF-chain of these roots. It distinguishes between single-USE and multi-USE scenarios for transformations, impacting analysis cost and optimization opportunities. The pass's behavior is controlled by flags like -fno-fold-mem-offsets and -fexpensive-optimizations.
- DF
- Data Flow analysis, a technique used in compilers to gather information about the flow of data through a program. It typically involves iterating over program instructions multiple times to converge on a stable state.
- RTL-SSA
- Register Transfer Language Static Single Assignment. RTL is GCC's intermediate representation for machine instructions. SSA is a program representation where every variable is assigned exactly once, simplifying many compiler analyses and optimizations.
- fold-mem-offsets
- A compiler optimization pass that identifies and potentially simplifies memory accesses where the address is calculated as a base register plus a constant offset.
- DEF-chain
- In the context of SSA, a chain tracing the definition of a value to its subsequent uses. Analyzing the DEF-chain helps determine if a value can be safely modified or eliminated.
- INSN
- An 'instruction' in GCC's internal representation. INSNs represent low-level machine operations.