SH: Fix T bit set expressions of addc and subc insns.
Corrects the T bit handling for `addc` and `subc` instructions on the SH architecture.
This commit fixes issues related to the T (result sign) bit in the instruction set for the SH architecture, specifically for the addc (add with carry) and subc (subtract with carry) instructions. The associated machine description patterns have been updated to correctly set or use the T bit, resolving bugs reported in PR target/67459 and PR target/122948. A new test case is included to verify the fix.
In Details
Fixes inaccuracies in the T-bit (carry flag) set expressions for addc and subc instructions in config/sh/sh.md, addressing PRs target/67459 and target/122948. This ensures the condition code register correctly reflects the outcome of these arithmetic operations, which is crucial for subsequent conditional branches and flag-dependent instructions.
- T bit
- A flag in the status register of some architectures (like SH) that indicates the result of an arithmetic operation. It often corresponds to the sign bit or a carry/borrow bit.
- addc
- An 'add with carry' instruction. It adds two operands plus the value of the carry flag from a previous operation.
- subc
- A 'subtract with carry' instruction. It subtracts two operands and the value of the borrow flag (often represented by the carry flag) from a previous operation.
- machine description
- Configuration files within GCC (e.g.,
.mdfiles) that describe the instruction set, addressing modes, and other target-specific details of a CPU architecture.