x86-64: Add missing SSE and AVX zero-extend patterns
Includes necessary SSE and AVX patterns for zero-extend conversion instructions, fixing PR target/126231.
GCD has added missing instruction generation patterns for zero-extending conversions using SSE and AVX instructions on x86-64. These new patterns cover various conversion types like cvtsh2si and cvtsd2usi with specific rounding modes. The change also includes new test cases to verify the correctness of these patterns.
In Details
This patch adds missing *_zext (zero-extend) and *_saeonly_zext patterns to i386.md and sse.md for SSE and AVX instructions, targeting PR target/126231. Specifically, it introduces round_zext and round_saeonly_zext generic patterns in subst.md and then utilizes them for various vcvt and cvt conversions involving sh, ss, sd to integer types (si, usi), including AVX512FP16 and AVX10 variants. New tests cover these additions.
- SSE
- Streaming SIMD Extensions. A set of SIMD instructions for x86 processors, designed for parallel processing of data.
- AVX
- Advanced Vector Extensions. An extension to SSE instructions that increases the number of registers and introduces new instructions for wider data processing.
- zero-extend
- A type of data conversion operation where bits beyond the most significant bit of the source value are set to zero. This is in contrast to sign-extend, where the most significant bit is duplicated.
- Pattern
- In compiler internals, a pattern represents a computational construct (like an arithmetic operation) that can be matched to one or more machine instructions.
- x86-64
- A 64-bit version of the x86 instruction set architecture.