RISC-V: Add minimal support for Svrsw60t59b extension.
GCC now recognizes the RISC-V Svrsw60t59b extension, related to page-table software bits.
This commit introduces minimal support for the RISC-V Svrsw60t59b extension, which defines reserved bits within page-table entries for software use. This extension is slated to be part of the upcoming RVA23.1 specification. The changes involve adding the new extension to GCC’s internal definitions, an options file, and documentation, enabling the compiler to acknowledge and potentially utilize this hardware feature in future development.
In Details
Support for the Svrsw60t59b extension has been added to GCC's RISC-V target configuration. This extension provides bits in page-table entries (specifically bits 60 and 59 of the physical address, it seems) reserved for operating system or hypervisor software management. The inclusion in riscv-ext.def, riscv-ext.opt, and doc/riscv-ext.texi allows GCC to recognize this specific feature for targeting systems implementing the RVA23.1 standard or related profiles.
- RISC-V
- An open-standard Instruction Set Architecture (ISA) based on Reduced Instruction Set Computing principles, designed for modularity and extensibility.
- Svrsw60t59b extension
- A proposed or newly finalized RISC-V extension that reserves specific bits (60 and 59) in page-table entries for software-defined purposes, likely related to memory management or virtualization.
- RVA23.1
- RISC-V Architecture Profile 2023.1, a standardized configuration of RISC-V base integer and standard extension instructions, aimed at providing a common target for common software stacks.
- page-table
- A data structure used by a virtual memory system to store the mapping between virtual addresses and physical addresses. It is fundamental to memory management in modern operating systems.
- ISA
- Instruction Set Architecture. Defines the set of instructions that a processor can understand and execute.