Optimize bit manipulation for RISC-V, reducing instruction count.
Improved RISC-V code generation for bit manipulation sequences, reducing instruction count.
This commit introduces a new pattern in the RISC-V backend’s match.pd to optimize specific bit manipulation sequences. It targets constructs like (1 << N) & (1 << N) where shifts occur in different types. By collapsing these into a single bit set operation within the wider type, the code generation is significantly improved, reducing an instruction sequence from six to three on rv64gcb.
In Details
This patch adds a new pattern to gcc/config/riscv/match.pd that recognizes and optimizes sequences forming (1 << N) & (1 << N) when the shifts operate on different types. The pattern aims to collapse such expressions into a single bit set instruction (1 << N) in the wider type, significantly reducing the instruction count. This addresses a specific performance issue reported for the RISC-V port, particularly for rv64gcb where the reduction is from 6 to 3 instructions.
- match.pd
- A file used by GCC to define instruction patterns for pattern matching and optimization, allowing the compiler to recognize and transform specific code sequences into more efficient instructions.
- instruction count
- The total number of machine instructions generated by the compiler for a given piece of code. A lower count often, but not always, indicates better performance.
- rv64gcb
- A specific configuration of the RISC-V 64-bit architecture, likely including standard integer (I), multiplication/division (M), compressed instructions (C), and bit manipulation (B) extensions.