RISC-V: Declare TLSDESC clobbers for vector registers and CSRs per psABI
RISC-V TLSDESC resolver now correctly declares clobbered vector registers and CSRs per updated psABI.
The RISC-V TLSDESC (Thread-Local Storage Descriptor) mechanism’s clobber list has been updated to align with the latest psABI. This change ensures that when the V extension is enabled, the TLS resolver correctly accounts for clobbered vector registers and control and status registers (CSRs), preventing potential runtime issues.
In Details
The RISC-V psABI specifies register clobbering for the TLSDESC resolver. Historically, this included a0 and t0. The recent RISC-V psABI update (PR#496) mandates additional clobbering of all vector registers (via LMUL8 reg groups) and specific vector CSRs (vl, vtype, vxrm, vxstat) when the V extension is present. This patch updates the tlsdesc define_insn in riscv.md to reflect these new clobber requirements.
- TLSDESC
- Thread-Local Storage Descriptor. A mechanism used in some ABIs for accessing thread-local variables, often involving a lookup function to resolve the variable's address at runtime.
- psABI
- Platform-Specific Application Binary Interface. Defines conventions for how software is compiled and linked, including register usage, function calling conventions, and memory layout, for a specific platform.
- V extension
- The RISC-V Vector extension, which provides single-instruction, multiple-data (SIMD) processing capabilities.
- CSR
- Control and Status Register. Special registers in a processor used for controlling its operation or reporting its status.