rs6000 adds vector uncompress/unpack builtins for -mcpu=future
New vector uncompress and unpack intrinsics for rs6000 with -mcpu=future, supporting proposed Power processor instructions.
The rs6000 backend now supports proposed vector uncompress and unpack instructions for future Power processors, enabled by the -mcpu=future flag. This includes new RTL patterns, builtin function definitions, and overloaded interfaces for operations like vec_uncompresshn and vec_unpack_hsn_to_byte. These additions provide access to new SIMD capabilities, though the builtin names may change in the future.
In Details
rs6000 adds support for proposed vector uncompress and unpack instructions via RFC02691, enabled by -mcpu=future. New RTL patterns (UNSPEC_VUCMPRHN, etc.) and builtin definitions (rs6000-builtins.def) are introduced for operations working on nibbles, bytes, and halfwords. This offers early access to potential future Power ISA vector extensions, with the caveat that names might evolve.
- rs6000
- GCC's target name for IBM POWER and PowerPC architectures.
- builtins
- Special functions provided by the compiler that map to specific machine instructions or provide extended functionality beyond standard C/C++.
- intrinsics
- Special functions that map directly to specific processor instructions, providing low-level hardware access from high-level code.
- SIMD
- Single Instruction, Multiple Data. A type of parallel processing where a single instruction operates on multiple data points simultaneously, often used for multimedia and scientific computations.
- altivec.md
- A GCC file containing instruction patterns and definitions for the AltiVec (VMX) SIMD instruction set extension on PowerPC processors.