RISC-V: RVV register overlap allowed for v[sz]ext.vf4
RISC-V vector extension now permits register overlap for `(v)sext.vf4` instructions.
This commit modifies the RISC-V vector implementation to allow register overlap for vzext.vf4 and vsext.vf4 instructions, similar to how it’s handled for v[sz]ext.vf2. This change involves adding a new predicate function is_frac_vlmul_p and updating the riscv_v_widen_constraint_ok function and vector machine description to accommodate these overlapping register constraints.
In Details
The RISC-V vector implementation now permits register overlap for v[sz]ext.vf4 instructions, mirroring the behavior already supported for v[sz]ext.vf2. This is achieved by introducing a new predicate is_frac_vlmul_p in riscv-protos.h and riscv-v.cc to identify fractional vlmul modes, and by modifying riscv_v_widen_constraint_ok in riscv-v.cc to handle cases where the destination lmul is less than or equal to 1. The vector.md file is updated to leverage a new Wvr (Widen Register) constraint.
- RVV
- RISC-V Vector Extension, a set of instructions designed for high-performance parallel processing of data.
- v[sz]ext.vf4
- RISC-V Vector instructions for sign (sz=s) or zero (sz=z) extension of elements, operating on a vector register group specified by 'vf4'.
- vlmul
- Vector Length Multiplier in RISC-V V extension, which determines the actual vector register elements to be used, relative to the SEW (Standard Element Width).
- SEW
- Standard Element Width, the width of individual elements within a RISC-V vector register.