RISC-V: Allow RVV register overlap for v[sz]ext.vf8
Enables register overlap for RISC-V vector instructions v[sz]ext.vf8, similar to v[sz]ext.vf4.
The RISC-V vector extension (RVV) code generator has been updated to permit register overlap for the v[sz]ext.vf8 instructions. This change mirrors the behavior already implemented for v[sz]ext.vf4 and utilizes the Wvr constraint in the vector machine description to manage register usage.
In Details
This commit modifies the RISC-V vector backend to allow register overlap for v[sz]ext.vf8 instructions. By leveraging the Wvr constraint in config/riscv/vector.md, the compiler can now reuse vector registers more aggressively for these operations, similar to how it handles v[sz]ext.vf4. This change aims to improve register utilization and potentially enable more efficient code generation.
- v[sz]ext.vf8
- Refers to RISC-V Vector extension (RVV) instructions for creating vectors of 8 elements, either by zero-extending (
vzext) or sign-extending (vsext). The '.vf8' suffix specifies the destination vector operand size. - register overlap
- The practice of allowing multiple instructions to use the same physical registers, either concurrently or sequentially, without interference. This can improve register pressure and code density.
- RVV
- Abbreviation for RISC-V Vector extension, an optional set of instructions for the RISC-V architecture designed to perform parallel operations on vectors of data.
- Wvr constraint
- A constraint used in GCC's machine description files (like 'vector.md') that likely specifies requirements or properties related to vector registers (often referred to as 'v' registers). In this case, it's used to permit register overlap.
- config/riscv/vector.md
- A file within the GCC source tree that defines the instruction patterns, constraints, and properties for the RISC-V vector extension, guiding the code generation process.