rs6000: Build DMF accumulators using DMR insert operations
Future PowerPC Dense Math Facility accumulators will use new DMR insert operations.
GCC’s rs6000 backend is updated to build Dense Math Facility (DMF) accumulators using new Dense Math Register (DMR) insert operations rather than xxmtacc/xxmfacc. This change prepares for future PowerPC processors where accumulators will be backed by DMRs. It includes adding DMR register predicate support, enabling necessary VSX pair patterns under TARGET_DMF, and modifying accumulator assembly/disassembly to use accumulator operands and avoid older instructions when DMF is active.
In Details
This commit refactors the assembly and disassembly of Dense Math Facility accumulators on rs6000 for future PowerPC processors. It replaces the use of xxmtacc/xxmfacc with dm_insert512 and dm_insert1024 instructions when TARGET_DMF is enabled, ensuring accumulators are built directly in Dense Math Registers (DMRs). Predicate support for DMRs is added, and OOmode VSX pair patterns are enabled. The commit also modifies GIMPLE folding logic to avoid emitting xxmtacc/xxmfacc and adds ISA attributes for instruction scheduling.
- rs6000
- The GCC target backend for IBM's POWER and PowerPC processor families, including POWER ISA variants.
- DMF
- Dense Math Facility. A set of instructions and registers on certain future PowerPC architectures designed for high-performance matrix and high-precision floating-point operations.
- DMR
- Dense Math Register. Specialized registers within the DMF that hold data for mathematical operations.
- xxmtacc/xxmfacc
- Specific PowerPC instructions used for moving data to and from accumulator registers. This commit replaces their use with new DMR insert operations when the Dense Math Facility is enabled.
- GIMPLE
- GCC's internal three-address code representation. Transformations on GIMPLE are a major part of the compiler's optimization pipeline.
- VSX
- Vector-Scalar Extension. An instruction set extension for PowerPC architectures that provides advanced vector processing capabilities, including combined vector and scalar operations.