RISC-V: Improve IOR/XOR synthesis for expensive constant cases
RISC-V backend improves constant synthesis for IOR/XOR operations to better utilize C extension instructions.
The RISC-V backend now uses riscv_integer_cost instead of riscv_const_insns for synthesizing IOR and XOR operations with expensive constants. This change enables the use of C extension instructions like XNOR, ORN, and ANDN, which can improve code generation when constants require more than three instructions to synthesize, preventing previously observed suboptimal code by distinguishing costs.
In Details
The synthesize_ior_xor function in riscv.cc now uses riscv_integer_cost to determine the cost of synthesizing constants for IOR/XOR operations. Previously, riscv_const_insns returned 0 for constants requiring >3 instructions, hindering optimization. Using riscv_integer_cost allows for better selection of C extension instructions (XNOR, ORN, ANDN) when the inverted constant has a lower cost than the original, even if both exceed the 3-instruction limit.
- IOR
- Inclusive OR, a bitwise logical operation that outputs 1 if any of the bits are 1.
- XOR
- Exclusive OR, a bitwise logical operation that outputs 1 if the bits are different.
- C extension instructions
- In RISC-V, these are instructions provided by the 'C' extension, which offer compressed instruction encoding and often perform operations like bitwise logical functions more efficiently.
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computing principles, widely used in embedded systems and accelerators.