RISC-V: Remove zama16b from xt-c9501fdvt
RISC-V '-mcpu=xt-c9501fdvt' no longer enables zama16b extension due to binutils support issues.
The RISC-V ‘-mcpu=xt-c9501fdvt’ configuration has been updated to exclude the ‘zama16b’ extension. This change is necessary because the assembler (binutils) does not yet support this extension, preventing successful compilation. A corresponding test case is adjusted to reflect that ‘__riscv_zama16b’ will be undefined.
In Details
The xt-c9501fdvt RISC-V CPU definition in riscv-cores.def incorrectly advertised support for the __riscv_zama16b extension. This commit removes it to align with the current capabilities of the binutils assembler, preventing compilation errors when this -mcpu option is used. The testsuite is updated to expect the absence of this macro.
- RISC-V
- An open-standard instruction set architecture (ISA). GCC supports various RISC-V configurations and extensions.
- zama16b
- A specific extension for the RISC-V architecture, likely related to address manipulation or memory access instructions.
- binutils
- A collection of binary tools, including the assembler (as), linker (ld), and other utilities, necessary for compiling and linking programs. GCC relies on binutils for assembling and linking object code.
- -mcpu=xt-c9501fdvt
- A GCC command-line option to specify a particular RISC-V processor variant or core, enabling a predefined set of extensions and optimizations for that core.