WEDNESDAY, JULY 15, 2026
risc-v
RISC-V: Adjust test case due to allow vwcvt[u].x.x.v overlap
RISC-V test cases adjusted after changes to vector convert instructions.
This commit adjusts RISC-V test cases by removing expected failures. The changes are related to the vwcvt[u].x.x.v vector instructions, which have been modified. The removal of xfail markers indicates that these instructions are now expected to function correctly according to the updated specifications.
For Context
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computing principles. GCC supports various RISC-V profiles and extensions.
- vwcvt[u].x.x.v
- RISC-V Vector Extension instructions for widening and converting vector elements. The 'u' indicates an unsigned operation. These instructions are used for data type conversions within vector registers.
- xfail
- A marker in GCC's testsuite indicating a test case that is expected to fail. This is often used when a known issue exists or when a feature is not yet fully supported.