WEDNESDAY, JULY 15, 2026
gcc/testsuite
RISC-V: Add tests for vwcvt.x.x.v register overlap
New RISC-V test cases verify vwcvt.x.x.v instruction behavior with register overlap.
Adds a suite of new test cases to the RISC-V testsuite specifically for the vwcvt.x.x.v instruction. These tests focus on scenarios involving register group overlap, ensuring correct functionality when source and destination registers might coincide.
In Details
This commit adds autovectorization test cases for the RISC-V Vector extension, specifically targeting the vwcvt.x.x.v instruction. These tests exercise the instruction's behavior when the destination vector register vd overlaps with the source vector register vs2, a scenario that can be tricky for instruction schedulers and register allocators. The tests cover various element widths and vector lengths.