Use SBFIZ for widening signed pow2 multiplies on AArch64
Optimized widening signed multiplies by a power of two on AArch64 using SBFIZ.
GCC now rewrites widening conversions of signed multiplies by a positive power of two on AArch64. Instead of multiplying then sign-extending, the multiplicand is widened first, allowing the operation to be emitted as a single SBFIZ instruction. This optimization is valid because overflow in signed multiplication is undefined behavior.
In Details
A new function, aarch64_try_widen_mult_by_pow2, is introduced in the AArch64 backend. This function specializes conversion assignments where a signed integer is multiplied by a power of two. It refactors the operation to widen the multiplicand before multiplication, enabling the use of the SBFIZ (Sign bit fill then zero) instruction and eliminating a separate sign-extension step. This optimization leverages the undefined nature of signed overflow.
- AArch64
- The 64-bit ARM architecture. GCC supports compiling code for this popular architecture.
- SBFIZ
- A specific AArch64 instruction that performs a signed bit fill from a source register into a destination register, followed by zeroing. It's useful for certain widening conversion operations.
- Widening conversion
- Converting a value from a smaller data type to a larger data type. For signed integers, this typically involves sign extension to preserve the value's sign.
- GIMPLE
- GCC's Internal Representation for General Intermediate Language. It's a three-address code form used within GCC for optimization passes.