RISC-V: Remove scratch register from bitfield extract splitter.
RISC-V bitfield extraction optimized by removing an unnecessary scratch register, reducing pressure on register allocation.
The RISC-V backend of GCC has optimized the bitfield extract instruction splitter. By removing an unnecessary early-clobber scratch register, the intermediate shift-left operation can now directly use its destination register. This change simplifies the generated code and reduces register pressure.
In Details
In config/riscv/riscv.md, the *<any_extract:optab><GPR:mode>3 pattern for bitfield extraction was using an unnecessary scratch register for the slli operation. Since slli reads its source *before* writing the destination, the destination register (operand 0) can safely hold the intermediate shifted result, eliminating the need for a separate scratch register and reducing register pressure.
- RISC-V
- An open-source instruction set architecture (ISA) that is modular and extensible.
- bitfield extract
- An operation that extracts a contiguous sequence of bits from a larger word.
- scratch register
- A temporary general-purpose register used by a function or code sequence for intermediate calculations, whose contents may not be preserved across calls or operations.
- early-clobber
- A constraint in some assembler or instruction generation contexts indicating that an output operand is written early, potentially affecting other operations within the same instruction or sequence.
- register pressure
- A measure of how many registers are simultaneously live and in use by a program, indicating the demand on the limited available registers.
- slli
- Shift Left Logical Immediate, an instruction that shifts bits to the left by a specified immediate value.