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JULY 29, 2026
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gcc Performance Win

Utilize shNadd.uw during ADD synthesis

Enhances RISC-V ADD instruction synthesis by using the shNadd.uw instruction for specific constants.

This patch improves the GCC compiler’s code generation for RISC-V architectures by enabling the use of the shNadd.uw instruction during the synthesis of addition operations. This instruction is particularly useful for additions involving constants where a shifted zero-extended value is involved. The change allows for more efficient instruction sequences, replacing a sequence of li and slli.uw with a single sh1add.uw for certain constants, such as src + 0x1ffffe000.

In Details

The RISC-V backend's ADD synthesis was enhanced to leverage the shNadd.uw instruction, which performs a shifted add after zero-extending the shifted operand. This is particularly relevant for constants C where x + C involves a shifted half of 0xFFFFFFFF. The existing mvconst_internal pass complicated direct pattern matching by expanding constants, so this change integrates shNadd.uw more directly into the ALU synthesis. The change targets specific constants where lui + slli.uw can be replaced by lui + shNadd.uw.

For Context
RISC-V
An open-standard instruction set architecture (ISA) based on reduced instruction set computing principles, popular for embedded systems and custom accelerators.
shNadd.uw
A RISC-V assembly instruction that performs a shifted-AND-add operation, where the shifted operand is zero-extended from a smaller integer type to a larger one before the addition. The '.uw' suffix specifically indicates unsigned word (32-bit to 64-bit) zero-extension.
ADD synthesis
The process within the compiler's code generation phase where high-level addition operations are translated into specific machine instructions.
RTL (Register Transfer Language)
An intermediate representation used internally by GCC to describe program operations at a level between the high-level source code and the target machine instructions.
lui
Load Upper Immediate. A RISC-V instruction used to load a 20-bit immediate value into the upper bits of a register, typically used in conjunction with other instructions to form larger constants.
Filed Under: RISC-Voptimizationcode generation