RISC-V: Use ordered scatter variants.
RISC-V vectorizer now uses ordered scatter operations, ensuring correct behavior for the vectorizer.
The RISC-V vectorizer has been updated to use ordered scatter variants instead of unordered ones. This change is necessary because the vectorizer expects scatter operations to write data in a specific, ordered sequence. By using the ordered indexed stores, the compiler ensures that this expectation is met, thereby improving the correctness and reliability of vector code generation for RISC-V.
In Details
The get_gather_scatter_code function in config/riscv/riscv-v.cc is modified to select ordered indexed store instructions over their unordered counterparts. This addresses PR target/126334, ensuring that scatter operations adhere to the ordered write semantics required by the vectorizer infrastructure. Test expectations for several gather/scatter test cases are adjusted to reflect this change.
- RISC-V
- An open-standard instruction set architecture (ISA) based on RISC principles, gaining popularity for its modularity and extensibility, especially in embedded systems and accelerators.
- vectorizer
- A compiler component that automatically transforms scalar code (operating on single data items) into vector code (operating on multiple data items simultaneously using special SIMD instructions). This can significantly improve performance for data-parallel tasks.
- scatter operation
- A memory access operation in vector processing where multiple data elements from a contiguous source are written to potentially non-contiguous memory locations specified by addresses in a separate index structure.
- ordered scatter
- A scatter operation where the memory writes occur in a defined sequence, typically corresponding to the order of elements in the source vector. This is crucial for certain compiler optimizations and hardware behaviors.