i386 reduction expansion honors preferred horizontal add
The i386 backend now better respects the `v2df_reduction_prefer_haddpd` option for vector reductions.
The i386 backend’s ix86_expand_reduc function now correctly honors the TARGET_V2DF_REDUCTION_PREFER_HADDPD option. This ensures that when this option is enabled, the expansion of reduc_plus_scal_V2DF operations prioritizes using the haddpd (horizontal packed double-precision add) instruction for better performance. A test case in gcc.target/i386/pr54400.c covers this functionality.
In Details
This commit modifies ix86_expand_reduc in i386-expand.cc to properly check and respect TARGET_V2DF_REDUCTION_PREFER_HADDPD. Previously, this target flag, which signals a preference for using horizontal additions for V2DF (two double-precision vector) reductions, might not have been consistently honored. The change ensures that gen_sse3_haddv2df3 is used when this target flag is set, optimizing the reduction of double-precision vectors by leveraging efficient horizontal instructions.
- i386
- Refers to the 32-bit x86 instruction set architecture, commonly associated with Intel processors. GCC targets this architecture and its extensions.
- SSE3
- Streaming SIMD Extensions 3, a set of instructions for x86 processors that enhance single-instruction, multiple-data (SIMD) processing capabilities, particularly for floating-point operations.
- horizontal packed double-precision add
- An SSE3 instruction (
haddpd) that performs addition operations on adjacent double-precision floating-point values within a vector register. This is a 'horizontal' operation as it combines elements across lanes, rather than performing 'vertical' operations within lanes. - vector reduction
- An operation that combines all elements of a vector into a single scalar value, typically through repeated addition, multiplication, or other associative operations. For example, summing all elements in a vector.