i386: Prefer shorter fold-left reduction chains
Improve loop vectorization cost model for FP reductions on x86.
This commit enhances the i386 vectorization cost model to prefer shorter instruction chains for floating-point reductions. Previously, wider vector modes could be chosen even if they increased the serial reduction chain length, impacting performance. The changes introduce a new metric to count reduction lanes, influencing loop candidate selection and preventing emulated sub-SSE modes from winning solely on this preference.
In Details
The ix86_vector_costs in i386 backend now incorporates a cost preference for shorter VEC_REDUC_PLUS_FIRST/LAST chains. This addresses a heuristic where wider vector modes might be chosen for FP reductions due to per-statement costs, even if they lengthen the VEC_REDUC_MAX chain. The better_fold_left_reduc_than_p function and associated lane counting in finish_cost refine loop selection. This avoids suboptimal choices when emulated sub-SSE modes are involved.
- fold-left reduction
- A loop pattern where an accumulator is updated iteratively with elements from a data structure. In vectorization, these can be complex to map efficiently to SIMD instructions.
- vectorization
- The process of converting scalar code sequences that operate on single data elements into equivalent code that operates on multiple data elements in parallel using SIMD (Single Instruction, Multiple Data) instructions.
- cost model
- A component of the compiler's optimizer that estimates the performance cost of different code sequences or execution strategies to guide optimization decisions.
- sub-SSE modes
- Refers to extended instruction set features on x86 processors that go beyond the original Streaming SIMD Extensions (SSE) instruction set, potentially including AVX, AVX2, etc. 'Emulated' suggests these might be compiled down to sequences that don't fully utilize the hardware capabilities.