RISC-V: Align vwcvt[u].x.x.v with vsext.vf8 register overlap rules
RISC-V vector extension allows register overlap for vwcvt[u].x.x.v instructions, similar to vsext.vf8.
This change allows the RISC-V vector extension’s vwcvt[u].x.x.v instructions to utilize register overlap. By leveraging the Wvr constraint in the vector instruction definition, the compiler can now generate code where the destination vector register set overlaps with the source register set, similar to the existing behavior of v[sz]ext.vf8.
In Details
In RISC-V vector processing, register allocation and instruction scheduling can be simplified if register overlap is permitted. This commit modifies the vector instruction pattern for vwcvt[u].x.x.v in config/riscv/vector.md to accept the Wvr constraint. This constraint indicates that the destination vector register vd can alias with the source vector register vs2, improving code generation efficiency by reducing the need for intermediate register copies.
- vwcvt[u].x.x.v
- A RISC-V vector instruction for vector unsigned/signed convert from integer type to integer type with vector register destination. It takes a source vector register and writes to a destination vector register.
- register overlap
- In processor instruction sets, register overlap occurs when an instruction can use the same register for both an input source operand and an output destination operand. Allowing this can simplify code generation and improve performance by reducing register pressure.
- Wvr constraint
- A constraint in GCC's machine description files that specifies a reusable vector register, allowing destination registers to overlap with source registers for certain vector instructions on RISC-V.