RISC-V: New test cases for vsext.vf4 register overlap
Added RISC-V test cases for `vsext.vf4` to verify register group overlap behavior.
This commit adds a set of new test cases for the RISC-V vector instruction vsext.vf4. These tests are designed to check for correct behavior when the destination registers for vsext.vf4 operations overlap with subsequent registers, particularly across different vector element widths and mask factors.
In Details
Several new test cases are introduced for vsext.vf4 (vector sign-extend, float factor 4) in the RISC-V testsuite. These tests specifically scrutinize the 'group overlap' behavior, ensuring that instructions that might use destination registers that partially or fully overlap with registers used by subsequent operations are handled correctly according to the RISC-V V extension specification.
- vsext.vf4
- RISC-V Vector instruction for sign-extending elements to a wider format. The '.vf4' indicates an operation involving four vector elements.
- register group overlap
- In the context of RISC-V vectors, this refers to situations where an operation on a vector of a certain length (e.g.,
vf4) might consume or alias registers that would also be used by subsequent operations, even if those subsequent operations are not immediately adjacent in the instruction stream.