RISC-V atomic load sequences improved
RISC-V atomic load sequences are optimized to remove redundant instructions and improve constraint handling.
This commit optimizes atomic load sequences on RISC-V architectures, particularly for RV64. It eliminates redundant sign extensions and improves address arithmetic. New constraints and iterators are introduced to correctly handle memory model acquire semantics and target-specific features like ZALRSC, ensuring generated code is more efficient and correct across different configurations.
In Details
This patch refactors RISC-V atomic load patterns in constraints.md and sync-rvwmo.md. It addresses PR target/124741 by removing redundant sext.w instructions after lw loads, and by combining address calculation into the load instruction itself. New constraints (B1-B4) and an iterator (cond_extend) are introduced to accurately model the interaction between memory ordering (MEMMODEL_ACQUIRE), the ZALASR/ZALRSC extensions, and the modes of atomic operations, ensuring correct generation of acquire semantics and preventing issues with zero-extension loads on ZALRSC-unsupported target…
- RISC-V
- An open-standard Instruction Set Architecture (ISA) based on Reduced Instruction Set Computing principles. It is modular and extensible, making it popular for embedded systems and high-performance computing.
- atomic operations
- Operations that are guaranteed to be performed indivisibly, without interruption from other threads or processes. They are crucial for concurrent programming to ensure data consistency.
- RV64
- The 64-bit version of the RISC-V instruction set architecture. It supports 64-bit pointers and general-purpose registers.
- ZALRSC / ZALASR
- RISC-V extensions related to atomic memory operations. ZALRSC (Atomic Loads and Reserved Store Conditional) and ZALASR (Atomic Loads and Reserved Store-Acquire) provide specific atomic primitives and memory ordering guarantees.