WEDNESDAY, JULY 8, 2026
gcc/risc-v
RISC-V: Scan asm for v[sz]ext.vf2 adjusted for v1/v12 overlap
RISC-V vector assembly tests refined to prevent incorrect matching of v12 with v1.
Assembly tests for RISC-V vector instructions vsext.vf2 and vzext.vf2 have been updated to correctly handle version numbers. A non-numeric boundary has been added to the match patterns to ensure that v12 is not mistakenly identified as v1, preventing incorrect instruction selection.
In Details
The assembly patterns used in test cases for vsext.vf2 and vzext.vf2 on RISC-V were too permissive. Previously, a pattern matching v1 could incorrectly match v12. This change adds a boundary condition to the pattern matching to strictly differentiate between version v1 and v12 in the scan assembly.
For Context
- scan asm
- A method for pattern matching within assembly code, often used in test suites to verify specific instruction sequences or operands.
- v[sz]ext.vf2
- RISC-V Vector extension instructions for sign/zero extension of vector elements, operating on a vector register group of size 2 (vf2).