RISC-V: Allow RVV register overlap for vfwcvt.rtz.x[u].f.v
RISC-V vector instructions vfwcvt.rtz.x[u].f.v now permit register overlap.
The RISC-V Vector extension now allows register overlap for the vfwcvt.rtz.x[u].f.v instructions, similar to how it’s handled for v[sz]ext.vf8. This change is implemented by updating the machine description to leverage the Wvr constraint, enabling more flexible register allocation and potentially improving code generation efficiency.
In Details
This commit updates the RISC-V vector machine description by allowing register overlap for the vfwcvt.rtz.x[u].f.v instructions. It achieves this by using the Wvr constraint in config/riscv/vector.md. This relaxation permits target register reuse, mirroring similar behavior already established for other vector extension instructions like v[sz]ext.vf8. The implication is that the backend can now schedule these conversion operations more aggressively, potentially reducing register pressure.
- vfwcvt.rtz.x[u].f.v
- RISC-V vector instructions for converting fixed-point to floating-point vectors. 'rtz' specifies round-to-nearest-even, ties-to-zero rounding. 'x' denotes signed integer input, 'u' denotes unsigned integer input.
- RVV
- RISC-V Vector extension, a set of instructions for processing data in vectors.
- register overlap
- A situation where instructions can reuse or share vector registers, enabling more efficient scheduling and reducing the need for distinct register allocations.
- Wvr constraint
- A machine constraint in GCC's target description language, likely related to the 'v' register class or a specific type of vector register usage in the RISC-V backend.