RISC-V: Allow RVV register overlap for vfwcvt.f.x[u] instructions
The RISC-V Vector extension now allows register overlap for `vfwcvt.f.x.v` and `vfwcvt.f.xu.v` instructions, improving flexibility in register allocation.
The GCC RISC-V backend now permits register overlap for the vfwcvt.f.x.v and vfwcvt.f.xu.v instructions. This change mirrors similar allowances for other vector instructions like vsext.vf8 and vszext.vf8, providing the compiler with more flexibility in register allocation and potentially enabling more efficient code generation for these vector conversion operations.
In Details
In config/riscv/vector.md, the Wvr constraint has been leveraged to allow register overlap for vfwcvt.f.x.v and vfwcvt.f.xu.v instructions. This change aligns the handling of these widening conversion instructions with other vector instructions in the RISC-V Vector extension (RVV) that already support register overlap, simplifying the backend's internal logic and potentially improving register utilization.
- RISC-V Vector extension (RVV)
- An extension to the RISC-V ISA that enables SIMD operations on vectors of data. It offers flexible control over vector length and register usage.
- `vfwcvt.f.x.v` / `vfwcvt.f.xu.v`
- These are RISC-V Vector extension instructions. They perform a widening conversion of integer vector elements to floating-point vector elements. The
xin the name typically indicates a signed integer source, andxuindicates an unsigned integer source. The.vsuffix indicates vector operations. - Register overlap
- In the context of vector instructions, register overlap refers to scenarios where a single instruction or a sequence of instructions might use registers that partially or fully overlap. Allowing overlap can sometimes enable more efficient instruction scheduling or code generation, but requires careful handling by the compiler.
- Wvr constraint
- A constraint used within GCC's machine description files (like
.mdfiles) that specifies requirements for operand registers, in this case, related to VSX registers or Vector registers in the RISC-V context, often involving specific alignment or grouping properties.