FRIDAY, JULY 3, 2026
sh
SH: Fix PR 124778
Corrects instruction pattern ordering to fix a pass bailout on the SH target.
This commit addresses a crash in the decompose_multiword_subregs pass on the SH architecture, caused by an incorrect ordering of instruction patterns in the machine description. By reordering specific extend<mode>si2 patterns, the pass now proceeds correctly, resolving the issue reported in PR 124778.
In Details
Fixes a bailout in the decompose_multiword_subregs pass for the SH target by reordering instruction patterns in config/sh/sh.md. The specific issue arose from an incorrect ordering of extend<mode>si2_short_mem_disp_z relative to *extend<mode>si2_compact_mem_disp, which caused the pass to fail when processing certain memory-disp register extensions.
For Context
- pass
- A distinct stage or transformation phase within the compiler's pipeline, operating on the intermediate representation or machine code. Examples include optimization passes, register allocation, and instruction scheduling.
- decompose_multiword_subregs
- A compiler pass responsible for breaking down operations involving multi-word registers (registers that hold more than one machine word) into operations on smaller sub-registers. This is often necessary for architectures with specific register constraints or instruction formats.
- instruction pattern
- A description in a machine description file that defines a specific assembly instruction or a sequence of instructions, including their operands, opcodes, and how they are generated from intermediate representations.
- register ordering
- The sequence in which assembly instructions or patterns are defined or matched within a machine description. Incorrect ordering can lead to ambiguity or failures in compiler passes that rely on pattern matching.