WEDNESDAY, JULY 8, 2026
gcc/risc-v
RISC-V: New test cases for vzext.vf4 register overlap
Added test cases for RISC-V `vzext.vf4` instruction to cover register group overlap scenarios.
This commit introduces a suite of new test cases for the RISC-V vector instruction vzext.vf4. These tests specifically target scenarios involving register group overlap, ensuring correct behavior when the operand for vzext.vf4 occupies a portion of a larger vector register group.
In Details
New test cases have been added to the RISC-V testsuite to exercise vzext.vf4 (vector zero-extend, float factor 4) with various vector element widths and mask factors. These tests focus on the 'group overlap' behavior, where the destination register for the operation may overlap with subsequent registers, ensuring correct semantic behavior and encoding.
For Context
- vzext.vf4
- RISC-V Vector instruction for zero-extending elements to a wider format, with '.vf4' indicating an operation involving four vector elements.
- register group overlap
- In the context of RISC-V vectors, this refers to situations where an operation on a vector of a certain length (e.g.,
vf4) might consume or alias registers that would also be used by subsequent operations, even if those subsequent operations are not immediately adjacent in the instruction stream.