RISC-V: Allow RVV register overlap for v[sz]ext.vf2
Enables RISC-V compiler to consider register overlap for widening vector instructions.
This commit updates the RISC-V backend to allow for register overlap in widening operations like vzext.vf2 and vsext.vf2, conforming to the RVV 1.0 specification. It renames constraints and adjusts register allocation logic to consider available overlapping register pairs, improving potential register utilization.
In Details
The RISC-V Vector Extension (RVV) specification permits source register overlap in widening instructions (e.g., vzext.vf2, vsext.vf2) where the destination element width exceeds the source. This patch modifies GCC's instruction selection and register allocation (LRA) on RISC-V to recognize and potentially utilize these overlapping register constraints, which were previously not fully exploited by the LRA. This involves changes to constraint definitions and helper functions in the backend.
- vzext.vf2
- A RISC-V vector instruction for zero-extension and widening, where the destination register group can partially overlap with the source register.
- vsext.vf2
- A RISC-V vector instruction for sign-extension and widening, where the destination register group can partially overlap with the source register.
- RVV
- The RISC-V Vector Extension, which provides instructions for SIMD (Single Instruction, Multiple Data) operations on vectors of data.
- Register overlap
- A situation where a single hardware register can be used for multiple purposes or as part of different data structures simultaneously, often to improve efficiency or code density.
- LRA
- Local Register Allocation, a phase in the compiler that assigns physical registers to intermediate or virtual registers.
- Constraint
- In compiler optimization and instruction selection, a rule or condition that must be met for a transformation or code generation to occur.